# FPGA Hardware Accelerator Pipeline on PolarFire SoC

## Project Description
This project implements an efficient data transfer pipeline between DDR memory and FPGA processing logic on the Microchip PolarFire SoC Icicle Kit. The goal is to offload data movement from the CPU to dedicated DMA hardware, minimizing CPU involvement and enabling hardware acceleration.

## System Architecture
```
DDR Memory [A] --> MM2S (protoconv1) --+
                                       +--> AXIS_ADDER --> S2MM (protoconv0) --> DDR Memory [C]
DDR Memory [B] --> MM2S (protoconv0) --+
```

## Components

### Hardware (FPGA)
- **axis_adder.v**: Custom Verilog module that adds two AXI-Stream inputs
- **CoreAXI4PROTOCONV**: Two protocol converter instances for DMA operations
- **CoreAXI4INTERCONNECT**: Two interconnects (FIC0 for control, DMA for data)

### Software (Linux)
- **axis_adder_ours.cpp**: C++ userspace driver using UIO framework
- **Device Tree**: Custom entries for protoconv0 and protoconv1

## Hardware Addresses
| Device | Address | Function |
|--------|---------|----------|
| protoconv0 | 0x60010000 | MM2S (input B) + S2MM (output C) |
| protoconv1 | 0x60011000 | MM2S (input A) |

## DDR Memory Layout
| Array | Address | Content |
|-------|---------|---------|
| A | 0xC8000000 | Input array A |
| B | 0xC8002000 | Input array B |
| C | 0xC8004000 | Output array C = A + B |

## How to Build and Run

### 1. Program FPGA
- Open Libero SoC project
- Generate bitstream
- Program using FlashPro via J33 JTAG connector

### 2. Prepare Linux
- Build Linux using Buildroot for RISC-V
- Add device tree entries for protoconv0 and protoconv1
- Write SD card image

### 3. Boot and Run
```bash
# Boot the Icicle Kit with SD card
# Login as root

# Verify UIO devices
ls /dev/uio*
cat /sys/class/uio/uio0/name  # Should show protoconv0
cat /sys/class/uio/uio1/name  # Should show protoconv1

# Compile and run
g++ axis_adder_ours.cpp -o axis_adder
./axis_adder
```

## Expected Output
```
locating device for protoconv0
locating device for protoconv1
located /dev/uio0
located /dev/uio1
MM2S version 3.0
MM2S version 3.0
S2MM version 3.0
S2MM_STS = 0x1
MM2S0_STS = 0x1
MM2S1_STS = 0x1
```

## Project Structure
```
FPGA_Project_Submission/
├── hardware/
│   └── axis_adder.v          # Custom Verilog adder module
├── software/
│   └── axis_adder_ours.cpp   # C++ userspace driver
├── device_tree/
│   └── mpfs-icicle-kit-fabric.dtsi  # Device tree modifications
├── docs/
│   └── (presentation materials)
└── README.md
```

## Author
Sofi Tshughuryan

## Course
Intro to Programming

## Date
20/05/26