//: version "2.1"
//: property encoding = "utf-8"
//: property locale = "en"
//: property prefix = "_GG"
//: property timingViolationMode = 2
//: property initTime = "0 ns"

`timescale 1ns/1ns

//: /netlistBegin main
module main;    //: root_module
reg w6;    //: /sn:0 {0}(109,100)(170,100){1}
reg w7;    //: /sn:0 {0}(107,251)(170,251){1}
wire w3;    //: /sn:0 {0}(323,100)(338,100)(338,86){1}
wire w2;    //: /sn:0 {0}(336,223)(336,238)(323,238){1}
//: enddecls

  //: SWITCH g4 (w7) @(90,251) /sn:0 /w:[ 0 ] /st:1 /dn:1
  //: SWITCH g3 (w6) @(92,100) /sn:0 /w:[ 0 ] /st:1 /dn:1
  //: LED g2 (w3) @(338,79) /sn:0 /w:[ 1 ] /type:0
  //: LED g1 (w2) @(336,216) /sn:0 /w:[ 0 ] /type:0
  RS_Latch g0 (.R(w6), .S(w7), .Q(w3), .Q0(w2));   //: @(171, 76) /sz:(151, 219) /sn:0 /p:[ Li0>1 Li1>1 Ro0<0 Ro1<1 ]

endmodule
//: /netlistEnd

//: /netlistBegin RS_Latch
module RS_Latch(Q, S, R, Q0);
//: interface  /sz:(151, 219) /bd:[ Li0>S(53/66) Li1>R(16/146) Ro0<Q0(49/66) Ro1<Q(16/146) ] /pd: 0 /pi: 0 /pe: 1 /pp: 1
output Q0;    //: /sn:0 {0}(145,143)(220,143){1}
//: {2}(224,143)(307,143)(307,142)(310,142){3}
//: {4}(222,141)(222,87)(112,87)(112,72)(122,72){5}
output Q;    //: /sn:0 {0}(143,70)(242,70){1}
//: {2}(246,70)(309,70){3}
//: {4}(244,72)(244,125)(114,125)(114,140)(124,140){5}
input R;    //: /sn:0 {0}(122,67)(37,67){1}
input S;    //: /sn:0 {0}(38,145)(124,145){1}
//: enddecls

  //: OUT g4 (Q) @(306,70) /sn:0 /w:[ 3 ]
  //: IN g3 (S) @(36,145) /sn:0 /w:[ 0 ]
  //: IN g2 (R) @(35,67) /sn:0 /w:[ 1 ]
  _GGNOR2 #(4) g1 (.I0(Q), .I1(S), .Z(Q0));   //: @(135,143) /sn:0 /w:[ 5 1 0 ]
  //: joint g6 (Q) @(244, 70) /w:[ 2 -1 1 4 ]
  //: joint g7 (Q0) @(222, 143) /w:[ 2 4 1 -1 ]
  //: OUT g5 (Q0) @(307,142) /sn:0 /w:[ 3 ]
  _GGNOR2 #(4) g0 (.I0(R), .I1(Q0), .Z(Q));   //: @(133,70) /sn:0 /w:[ 0 5 0 ]

endmodule
//: /netlistEnd