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FPGA Hardware Accelerator Pipeline on PolarFire SoC

Hardware Acceleration | DMA | AXI-Stream

An efficient data transfer pipeline between DDR memory and FPGA processing logic on the Microchip PolarFire SoC Icicle Kit. The project offloads data movement from the CPU to dedicated DMA hardware, enabling hardware acceleration with minimal CPU involvement.

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Key Components

  • Custom Verilog adder module (AXI-Stream)
  • CoreAXI4PROTOCONV DMA engines
  • Linux UIO driver integration
  • C++ userspace application
  • Device tree configuration
  • Buildroot Linux system

Technologies

  • Microchip PolarFire SoC
  • Libero SoC Design Suite
  • Verilog HDL
  • C++ / Linux
  • AXI4 / AXI-Stream protocols
  • RISC-V architecture

Project Files

.v
axis_adder.v
Custom Verilog AXI-Stream adder module
.cpp
axis_adder_ours.cpp
C++ userspace driver using UIO framework
.dtsi
mpfs-icicle-kit-fabric.dtsi
Device tree with protoconv entries
MD
README.md
Project documentation